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? 2009-2011 microchip technology inc. ds22188c-page 1 mcp621/1s/2/3/4/5/9 features ? gain bandwidth product: 20 mhz (typical) ? short circuit current: 70 ma (typical) ? noise: 13 nv/ hz (typical, at 1 mhz) ? calibrated input offset: 200 v (maximum) ? rail-to-rail output ? slew rate: 10 v/s (typical) ? supply current: 2.5 ma (typical) ? power supply: 2.5v to 5.5v ? extended temperature range: -40c to +125c typical applications ? driving a/d converters ? power amplifier control loops ? barcode scanners ? optical detector amplifier design aids ? spice macro models ?filterlab ? software ? microchip advanced part selector (maps) ? analog demonstration and evaluation boards ? application notes description the microchip technology, inc. mcp621/1s/2/3/4/5/9 family of operational amplifiers features low offset. at power-up, these op amps are self-calibrated using mcal. some package options also provide a calibra- tion/chip select pin (cal/cs ) that supports a low- power mode of operation, with offset calibration at the time normal operation is re-started. these amplifiers are optimized for high speed, low noise and distortion, single-supply operation with rail-to-rail output and an input that includes the negative rail. this family is offered in single (mcp621 and mcp621s), single with cal/cs pin (mcp623), dual (mcp622), dual with cal/cs pins (mcp625), quad (mcp624) and quad with cal/cs pins (mcp629). all devices are fully specified from -40c to +125c. typical application circuit powerdriverwithhighgain r 1 r 2 v in v dd /2 v out r 3 r l mcp62x 20 mhz, 2.5 ma op amps with mcal
mcp621/1s/2/3/4/5/9 ds22188c-page 2 ? 2009-2011 microchip technology inc. package types mcp621 soic mcp622 soic v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 v cal cal/cs nc v ina + v ina ? v ss 1 2 3 4 8 7 6 5 v outa v dd v outb v inb ? v inb + mcp625 msop v ina + v ina ? v ss 1 2 3 4 10 9 8 7 v outa v dd v outb v inb ? v inb + cal a /cs a 5 6 cal b /cs b mcp622 3x3 dfn * mcp625 3x3 dfn * * includes exposed thermal pad (ep); see ta b l e 3 - 1 . v ina + v ina ? v ss v outb v inb ? 1 2 3 4 8 7 6 5 v inb + v dd v outa ep 9 v ss v ina + cal a /cs a v inb ? v inb + 2 3 4 5 9 8 7 6 cal b /cs b v outb v ina ? ep 11 1 10 v dd v outa 2 mcp629 4x4 qfn* v dd v inb + v ina -v ind + v ss v inb - v inc + v outb cal bc /cs bc v outc v inc - v outa cal ad /cs ad v outd v ind - v ina + ep 16 1 15 14 13 3 4 12 11 10 9 5678 17 mcp624 soic, tssop v ina + v ina - v dd 1 2 3 4 14 13 12 11 v outa v outd v ind - v ind + v ss v inb + 5 10 v inc + v inb - 6 9 v outb 7 8 v outc v inc - mcp621 2x3 tdfn * v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 v cal cal/cs nc ep 9 cal/cs v in + v out v ss v in - mcp623 sot-23-6 v dd 1 2 3 4 5 6 v in + v out v ss v in - mcp621s sot-23-5 v dd 1 2 3 4 5
? 2009-2011 microchip technology inc. ds22188c-page 3 mcp621/1s/2/3/4/5/9 1.0 electrical characteristics 1.1 absolute maximum ratings ? v dd ?v ss .......................................................................6.5v current at input pins ....................................................2 ma analog inputs (v in + and v in ?) ?? . v ss ? 1.0v to v dd +1.0v all other inputs and outputs ......... v ss ? 0.3v to v dd +0.3v output short circuit current ................................ continuous current at output and supply pins ..........................150 ma storage temperature ...................................-65c to +150c max. junction temperature ........................................ +150c esd protection on all pins (hbm, mm) ................ 1 kv, 200v ?notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ?? see section 4.2.2, input voltage and current limits . 1.2 specifications table 1-1: dc electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v cm = v dd /3, v out v dd /2, v l = v dd /2, r l = 2 k to v l and cal/cs =v ss (refer to figure 1-2 ). parameters sym min typ max units conditions input offset input offset voltage v os -200 ? +200 v after calibration ( note 1 ) input offset voltage trim step size v ostrm ?37200v ( note 2 ) input offset voltage drift v os / t a ?2.0?v/ct a = -40c to +125c power supply rejection ratio psrr 61 76 ? db input current and impedance input bias current i b ?5?pa across temperature i b ?100?pat a = +85c across temperature i b ? 1700 5,000 pa t a = +125c input offset current i os ?10?pa common mode input impedance z cm ?10 13 ||9 ? ||pf differential input impedance z diff ?10 13 ||2 ? ||pf common mode common mode input voltage range v cmr v ss ? 0.3 ? v dd ? 1.3 v ( note 3 ) common mode rejection ratio cmrr 65 81 ? db v dd = 2.5v, v cm = -0.3 to 1.2v cmrr 68 84 ? db v dd = 5.5v, v cm = -0.3 to 4.2v open-loop gain dc open-loop gain (large signal) a ol 88 117 ? db v dd = 2.5v, v out = 0.3v to 2.2v a ol 94 126 ? db v dd = 5.5v, v out = 0.3v to 5.2v note 1: describes the offset (under the specified conditions) right after power-up, or just after the cal/cs pin is toggled. thus, 1/f noise effects (an apparent wander in v os ; see figure 2-35 ) are not included. 2: increment between adjacent v os trim points; figure 2-3 shows how this affects the v os repeatability. 3: see figure 2-6 and figure 2-7 for temperature effects. 4: the i sc specifications are for design guidance only; they are not tested.
mcp621/1s/2/3/4/5/9 ds22188c-page 4 ? 2009-2011 microchip technology inc. output maximum output voltage swing v ol , v oh v ss +20 ? v dd ? 20 mv v dd = 2.5v, g = +2, 0.5v input overdrive v ol , v oh v ss +40 ? v dd ? 40 mv v dd = 5.5v, g = +2, 0.5v input overdrive output short circuit current i sc 40 85 130 ma v dd = 2.5v ( note 4 ) i sc 35 70 110 ma v dd = 5.5v ( note 4 ) calibration input calibration input voltage range v calrng v ss +0.1 ? v dd ?1.4 mv v cal pin externally driven internal calibration voltage v cal 0.323v dd 0.333v dd 0.343v dd v cal pin open input impedance z cal ?100||5?k ||pf power supply supply voltage v dd 2.5 ? 5.5 v quiescent current per amplifier i q 1.2 2.5 3.6 ma i o = 0 por input threshold, low v prl 1.15 1.40 ? v por input threshold, high v prh ? 1.40 1.65 v table 1-2: ac electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, v l = v dd /2, r l = 2 k to v l , c l = 50 pf and cal/cs =v ss (refer to figure 1-2 ). parameters sym min typ max units conditions ac response gain bandwidth product gbwp ? 20 ? mhz phase margin pm ? 60 ? g = +1 open-loop output impedance r out ?15? ac distortion total harmonic distortion plus noise thd+n ? 0.0018 ? % g = +1, v out = 2v p-p , f = 1 khz, v dd = 5.5v, bw = 80 khz step response rise time, 10% to 90% t r ? 13 ? ns g = +1, v out = 100 mv p-p slew rate sr ? 10 ? v/s g = +1 noise input noise voltage e ni ?20?v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ?13?nv/ hz f = 1 mhz input noise current density i ni 4?fa/ hz f = 1 khz table 1-1: dc electrical specifications (continued) electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v cm = v dd /3, v out v dd /2, v l = v dd /2, r l = 2 k to v l and cal/cs =v ss (refer to figure 1-2 ). parameters sym min typ max units conditions note 1: describes the offset (under the specified conditions) right after power-up, or just after the cal/cs pin is toggled. thus, 1/f noise effects (an apparent wander in v os ; see figure 2-35 ) are not included. 2: increment between adjacent v os trim points; figure 2-3 shows how this affects the v os repeatability. 3: see figure 2-6 and figure 2-7 for temperature effects. 4: the i sc specifications are for design guidance only; they are not tested.
? 2009-2011 microchip technology inc. ds22188c-page 5 mcp621/1s/2/3/4/5/9 table 1-3: digital electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, v l = v dd /2, r l = 2 k to v l , c l = 50 pf and cal/cs =v ss (refer to figure 1-1 and figure 1-2 ). parameters sym min typ max units conditions cal/cs low specifications cal/cs logic threshold, low v il v ss ?0.2v dd v cal/cs input current, low i csl ?0?nacal/cs = 0v cal/cs high specifications cal/cs logic threshold, high v ih 0.8v dd v dd v cal/cs input current, high i csh ? 0.7 ? a cal/cs = v dd gnd current i ss -3.5 -1.8 ? a single, cal/cs = v dd = 2.5v i ss -8 -4 ? a single, cal/cs = v dd = 5.5v i ss -5 -2.5 ? a dual, cal/cs = v dd = 2.5v i ss -10 -5 ? a dual, cal/cs = v dd = 5.5v cal/cs internal pull-down resistor r pd ?5?m amplifier output leakage i o(leak) ? 50 ? na cal/cs = v dd , t a = 125c por dynamic specifications v dd low to amplifier off time (output goes high-z) t poff ? 200 ? ns g = +1 v/v, v l = v ss , v dd = 2.5v to 0v step to v out =0.1 (2.5v) v dd high to amplifier on time (including calibration) t pon 100 200 300 ms g = +1 v/v, v l = v ss , v dd = 0v to 2.5v step to v out =0.9 (2.5v) cal/cs dynamic specifications cal/cs input hysteresis v hyst ? 0.25 ? v cal/cs setup time (between cal/cs edges) t csu 1??sg = +1v/v, v l = v ss ( notes 2 , 3 , 4 ) cal/cs = 0.8v dd to v out = 0.1 (v dd /2) cal/cs high to amplifier off time (output goes high-z) t coff ? 200 ? ns g = +1 v/v, v l = v ss , cal/cs = 0.8v dd to v out = 0.1 (v dd /2) cal/cs low to amplifier on time (including calibration) t con ?3 4ms g = +1 v/v, v l = v ss , mcp621 and mcp625, cal/cs = 0.2v dd to v out =0.9(v dd /2) t con ?6 8ms g = +1 v/v, v l = v ss , mcp629, cal/cs = 0.2v dd to v out =0.9(v dd /2) note 1: the mcp622 single, mcp625 dual and mcp629 quad have their cal/cs inputs internally pulled down to v ss (0v). 2: this time ensures that the internal logic recognizes the edge. however, for the rising edge case, if cal/cs is raised before the calibration is complete, the calibration will be aborted and the part will return to low-power mode. 3: for the mcp625 dual, there is an additional constraint. cal a /cs a and cal b /cs b can be toggled simultaneously (within a time much smaller than t csu ) to make both op amps perform the same function simultaneously. if they are toggled independently, then cal a /cs a (cal b /cs b ) cannot be allowed to toggle whil e op amp b (op amp a) is in calibration mode; allow more than the maximum t con time (4 ms) before the other side is toggled. 4: for the mcp629 quad, there is an additional constraint. cal ad /cs ad and cal bc /cs bc can be toggled simultaneously (within a time much smaller than t csu ) to make all four op amps perform the same function simultaneously, and the maximum t con time is approximately doubled (8 ms). if they are toggled independently, then cal ad /cs ad (cal bc /cs bc ) cannot be allowed to toggle while op amps b and c (op amps a and d) are in calibration mode; allow more than the maximum t con time (8 ms) before the other side is toggled.
mcp621/1s/2/3/4/5/9 ds22188c-page 6 ? 2009-2011 microchip technology inc. 1.3 timing diagram figure 1-1: timing diagram. table 1-4: temperature specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v dd = +2.5v to +5.5v,v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c ( note 1 ) storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot-23 ja ? 220.7 ? c/w thermal resistance, 6l-sot-23 ja ? 190.5 ? c/w thermal resistance, 8l-2x3 tdfn ja ?52.5?c/w thermal resistance, 8l-3x3 dfn ja ?56.7?c/w ( note 2 ) thermal resistance, 8l-soic ja ? 149.5 ? c/w thermal resistance, 10l-3x3 dfn ja ?53.3?c/w ( note 2 ) thermal resistance, 10l-msop ja ?202?c/w thermal resistance, 14l-soic ja ?95.3?c/w thermal resistance, 14l-tssop ja ?100?c/w thermal resistance, 16l-4x4-qfn ja ?45.7?c/w ( note 2 ) note 1: operation must not cause t j to exceed the maximum junction temperature specification (150c). 2: measured on a standard jc51-7, four layer printed circuit board with ground plane and vias. high-z v dd v out -3 a (typical) high-z i ss i cs -3 a (typical) -2.5 ma (typical) v prh v prl t pon t poff on 0na(typical) high-z -3 a (typical) -2.5 ma (typical) t coff t con on 0.7 a (typical) 0na(typical) cal/cs v ih v il t csu note: for the mcp625 dual and the mcp629 quad, there is an additional constraint on toggling the two cal/cs pins close together; see the t con specification in tab l e 1 - 3 .
? 2009-2011 microchip technology inc. ds22188c-page 7 mcp621/1s/2/3/4/5/9 1.4 test circuits the circuit used for most dc and ac tests is shown in figure 1-2 . this circuit can independently set v cm and v out ; see equation 1-1 . note that v cm is not the circuit?s common mode voltage ((v p +v m )/2), and that v ost includes v os plus the effects (on the input offset error, v ost ) of temperature, cmrr, psrr and a ol . equation 1-1: figure 1-2: ac and dc test circuit for most specifications. g dm r f r g ? = v cm v p v dd 2 ? + () 2 ? = v out v dd 2 ? () v p v m ? () v ost 1g dm + () ++ = where: g dm = differential mode gain (v/v) v cm = op amp?s common mode input voltage (v) v ost = op amp?s total input offset voltage (mv) v ost v in? v in+ ? = v dd r g r f v out v m c b2 c l r l v l c b1 10 k 10 k r g r f v dd /2 v p 10 k 10 k 50 pf 2k 2.2 f 100 nf v in? v in+ c f 6.8 pf c f 6.8 pf mcp62x
mcp621/1s/2/3/4/5/9 ds22188c-page 8 ? 2009-2011 microchip technology inc. notes:
? 2009-2011 microchip technology inc. ds22188c-page 9 mcp621/1s/2/3/4/5/9 2.0 typical performance curves note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . 2.1 dc signal inputs figure 2-1: input offset voltage. figure 2-2: input offset voltage drift. figure 2-3: input offset voltage repeatability (repeated calibration). figure 2-4: input offset voltage vs. power supply voltage. figure 2-5: input offset voltage vs. output voltage. figure 2-6: low input common mode voltage headroom vs. ambient temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% -80-60-40-20 0 20406080 input offset voltage (v) percentage of occurrences 80 samples t a = +25c v dd = 2.5v and 5.5v calibrated at +25c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 24% -10-8-6-4-20246810 input offset voltage drift (v/c) percentage of occurrences 80 samples v dd = 2.5v and 5.5v t a = -40c to +125c calibrated at +25c 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 input offset voltage calibration repeatability (v) percentage of occurrences 200 samples t a = +25c v dd = 2.5v and 5.5v calibration changed (-1 step) no change (includes noise) calibration changed (+1 step) -700 -600 -500 -400 -300 -200 -100 0 100 200 300 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) input offset voltage (v) +125c +85c +25c -40c representative part calibrated at v dd = 6.5v -50 -40 -30 -20 -10 0 10 20 30 40 50 0.00.51.01.52.02.53.03.54.04.55.05.5 output voltage (v) input offset voltage (v) v dd = 2.5v v dd = 5.5v representative part -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -50 -25 0 25 50 75 100 125 ambient temperature (c) low input common mode headroom (v) v dd = 2.5v 1 lot low (v cmr_l ? v ss ) v dd = 5.5v
mcp621/1s/2/3/4/5/9 ds22188c-page 10 ? 2009-2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . figure 2-7: high input common mode voltage headroom vs. ambient temperature. figure 2-8: input offset voltage vs. common mode voltage with v dd =2.5v. figure 2-9: input offset voltage vs. common mode voltage with v dd =5.5v. figure 2-10: cmrr and psrr vs. ambient temperature. figure 2-11: dc open-loop gain vs. ambient temperature. figure 2-12: input bias and offset currents vs. ambient temperature with v dd =+5.5v. 1.0 1.1 1.2 1.3 1.4 -50-25 0 255075100125 ambient temperature (c) high input common mode headroom (v) v dd = 2.5v v dd = 5.5v 1 lot high (v dd ? v cmr_h ) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 input common mode voltage (v) input offset voltage (v) v dd = 2.5v representative part +125c +85c +25c -40c -1000 -800 -600 -400 -200 0 200 400 600 800 1000 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 input common mode voltage (v) input offset voltage (v) v dd = 5.5v representative part +125c +85c +25c -40c 60 65 70 75 80 85 90 95 100 105 110 -50 -25 0 25 50 75 100 125 ambient temperature (c) cmrr, psrr (db) psrr cmrr, v dd = 5.5v cmrr, v dd = 2.5v 100 105 110 115 120 125 130 -50 -25 0 25 50 75 100 125 ambient temperature (c) dc open-loop gain (db) v dd = 5.5v v dd = 2.5v 1 10 100 1,000 10,000 25 45 65 85 105 125 ambient temperature (c) input bias, offset currents (pa) v dd = 5.5v v cm = v cmr_h | i os | i b
? 2009-2011 microchip technology inc. ds22188c-page 11 mcp621/1s/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . figure 2-13: input bias and offset currents vs. common mode input voltage with t a = +85c. figure 2-14: input bias and offset currents vs. common mode input voltage with t a = +125c. figure 2-15: input bias current vs. input voltage (below v ss ). -60 -40 -20 0 20 40 60 80 100 120 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input bias, offset currents (pa) i b representative part t a = +85c v dd = 5.5v i os -1000 -500 0 500 1000 1500 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias, offset currents (pa) i b representative part t a = +125c v dd = 5.5v i os 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 -1.0 -0.9 -0.8 -0.7 -0.6 -0 .5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) input current magnitude (a) +125c +85c +25c -40c 1m 100 10 1 100n 10n 1n 100p 10p 1p
mcp621/1s/2/3/4/5/9 ds22188c-page 12 ? 2009-2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . 2.2 other dc voltages and currents figure 2-16: ratio of output voltage headroom to output current. figure 2-17: output voltage headroom vs. ambient temperature. figure 2-18: output short circuit current vs. power supply voltage. figure 2-19: supply current vs. power supply voltage. figure 2-20: supply current vs. common mode input voltage. figure 2-21: power-on reset voltages vs. ambient temperature. 0 2 4 6 8 10 12 14 110100 output current magnitude (ma) ratio of output headroom to output current (mv/ma) v dd = 2.5v v dd = 5.5v v dd ? v oh i out v ol ? v ss -i out 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 ambient temperature (c) output headroom (mv) v dd = 5.5v v ol ? v ss v dd = 2.5v v dd ? v oh r l = 2 k ? -100 -80 -60 -40 -20 0 20 40 60 80 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) output short circuit current (ma) +125c +85c +25c -40c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) supply current (ma/amplifier) +125c +85c +25c -40c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) supply current (ma/amplifier) v dd = 2.5v v dd = 5.5v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 ambient temperature (c) por trip voltages (v) v prl v prh
? 2009-2011 microchip technology inc. ds22188c-page 13 mcp621/1s/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . figure 2-22: normalized internal calibration voltage. figure 2-23: v cal input resistance vs. temperature. 0% 5% 10% 15% 20% 25% 30% 33.20% 33.24% 33.28% 33.32% 33.36% 33.40% 33.44% 33.48% 33.52% normalized internal calibration voltage; v cal /v dd percentage of occurrences 144 samples v dd = 2.5v and 5.5v 0 20 40 60 80 100 120 140 -50-25 0 255075100125 ambient temperature (c) internal v cal resistance (k ? )
mcp621/1s/2/3/4/5/9 ds22188c-page 14 ? 2009-2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . 2.3 frequency response figure 2-24: cmrr and psrr vs. frequency. figure 2-25: open-loop gain vs. frequency. figure 2-26: gain bandwidth product and phase margin vs. ambient temperature. figure 2-27: gain bandwidth product and phase margin vs. common mode input voltage. figure 2-28: gain bandwidth product and phase margin vs. output voltage. figure 2-29: closed-loop output impedance vs. frequency. 10 20 30 40 50 60 70 80 90 100 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 1.e+7 frequency (hz) cmrr, psrr (db) cmrr 100 1m 10k 10m 100k 1k psrr+ psrr- -20 0 20 40 60 80 100 120 140 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 1.e+7 1.e+8 frequency (hz) open-loop gain (db) -240 -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () | a ol | a ol 10 1k 100k 10m 1 100 10k 1m 100m 15 20 25 30 35 40 45 -50-25 0 255075100125 ambient temperature (c) gain bandwidth product (mhz) 40 45 50 55 60 65 70 phase margin () pm gbwp v dd = 5.5v v dd = 2.5v 15 20 25 30 35 40 45 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) gain bandwidth product (mhz) 40 45 50 55 60 65 70 phase margin () pm gbwp v dd = 5.5v v dd = 2.5v 15 20 25 30 35 40 45 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) gain bandwidth product (mhz) 40 45 50 55 60 65 70 phase margin () pm gbwp v dd = 5.5v v dd = 2.5v 0.1 1 10 100 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 frequency (hz) 1k 1m 10m 100m open-loop output impedance ( ? ) 10k 100k g = 101 v/v g = 11 v/v g = 1 v/v
? 2009-2011 microchip technology inc. ds22188c-page 15 mcp621/1s/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . figure 2-30: gain peaking vs. normalized capacitive load. figure 2-31: channel-to-channel separation vs. frequency. 0 1 2 3 4 5 6 7 8 9 10 1.0e-11 1.0e-10 1.0e-09 normalized capacitive load; c l /g n (f) gain peaking (db) 10p 100p 1n g n = 1 v/ v g n = 2 v/ v g n 4 v/ v 50 60 70 80 90 100 110 120 130 140 150 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) channel-to-channel separation (db) 1k 10k 100k rti v cm = v dd /2 g = +1 v/v r s = 0 ? r s = 1 k ? r s = 10 k ? r s = 100 k ? 1m 10m
mcp621/1s/2/3/4/5/9 ds22188c-page 16 ? 2009-2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . 2.4 input noise and distortion figure 2-32: input noise voltage density vs. frequency. figure 2-33: input noise voltage density vs. input common mode voltage with f = 100 hz. figure 2-34: input noise voltage density vs. input common mode voltage with f = 1 mhz. figure 2-35: input noise plus offset vs. time with 0.1 hz filter. figure 2-36: thd+n vs. frequency. 1.e+1 1.e+2 1.e+3 1.e+4 1.e-1 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 1.e+7 frequency (hz) 0.1 100 10k 1m input noise voltage density (nv/ hz) 11k100k10m 10 10n 100n 1 10 0 50 100 150 200 250 300 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) v dd = 5.5v v dd = 2.5v input noise voltage density (nv/ hz) f = 100 hz 0 5 10 15 20 25 30 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) v dd = 5.5v v dd = 2.5v input noise voltage density (nv/ hz) f = 1 mhz -20 -15 -10 -5 0 5 10 15 20 0 5 10 15 20 25 30 35 40 45 time (min) input offset + noise; v os + e ni (t) (v) representative part analog npbw = 0.1 hz sample rate = 2 sps 0.0001 0.001 0.01 0.1 1 1.e+2 1.e+3 1.e+4 1.e+5 frequency (hz) thd + noise (%) v dd = 5.0v v out = 2 v p-p 100 1k 10k 100k bw = 22 hz to 80 khz bw = 22 hz to > 500 khz g = 1 v/v g = 11 v/v
? 2009-2011 microchip technology inc. ds22188c-page 17 mcp621/1s/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . 2.5 time response figure 2-37: non-inverting small signal step response. figure 2-38: non-inverting large signal step response. figure 2-39: inverting small signal step response. figure 2-40: inverting large signal step response. figure 2-41: the mcp621/1s/2/3/4/5/9 family shows no input phase reversal with overdrive. figure 2-42: slew rate vs. ambient temperature. 0 20 40 60 80 100 120 140 160 180 200 time (ns) output voltage (10 mv/div) v dd = 5.5v g = 1 v in v out 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 time (s) output voltage (v) v dd = 5.5v g = 1 v in v out 0 100 200 300 400 500 600 700 800 time (ns) output voltage (10 mv/div) v dd = 5.5v g = -1 r f = 1 k ? v in v out 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.00.20.40.60.81.01.21.41.61.82.0 time (s) output voltage (v) v dd = 5.5v g = -1 r f = 1 k ? v in v out -1 0 1 2 3 4 5 6 7 012345678910 time (ms) input, output voltages (v) v dd = 5.5v g = 2 v out v in 0 2 4 6 8 10 12 14 16 18 20 22 24 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) falling edge rising v dd = 2.5v v dd = 5.5v
mcp621/1s/2/3/4/5/9 ds22188c-page 18 ? 2009-2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . figure 2-43: maximum output voltage swing vs. frequency. 0.1 1 10 1.e+05 1.e+06 1.e+07 1.e+08 frequency (hz) maximum output voltage swing (v p-p ) v dd = 5.5 v v dd = 2.5 v 100k 1m 10m 100m
? 2009-2011 microchip technology inc. ds22188c-page 19 mcp621/1s/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . 2.6 calibration and chip select response figure 2-44: cal/cs current vs. power supply voltage. figure 2-45: cal/cs voltage, output voltage and supply current (for side a) vs. time with v dd =2.5v. figure 2-46: cal/cs voltage, output voltage and supply current (for side a) vs. time with v dd =5.5v. figure 2-47: cal/cs hysteresis vs. ambient temperature. figure 2-48: cal/cs turn-on time vs. ambient temperature. figure 2-49: cal/cs ?s pull-down resistor (r pd ) vs. ambient temperature. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) cal/cs current (a) cal/cs = v dd -1 0 1 2 3 4 5 6 7 8 0246810121416 time (ms) cal/cs, v out (v) -12 -10 -8 -6 -4 -2 0 2 4 6 power supply current; i dd (ma) v dd = 2.5v g = 1 v l = 0v op amp turns on cal/cs op amp turns off calibration starts i dd v out -2 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 time (ms) cal/cs, v out (v) -12 -10 -8 -6 -4 -2 0 2 4 6 power supply current; i dd (ma) v dd = 5.5v g = 1 v l = 0v op amp turns on cal/cs op amp turns off calibration starts i dd v out 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 ambient temperature (c) cal/cs hysteresis (v) v dd = 2.5v v dd = 5.5v 0 1 2 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 ambient temperature (c) cal/cs turn on time (ms) 0 1 2 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 ambient temperature (c) cal/cs pull-down resistor (m ? ) representative part
mcp621/1s/2/3/4/5/9 ds22188c-page 20 ? 2009-2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k to v l , c l = 50 pf, and cal/cs =v ss . figure 2-50: quiescent current in shutdown vs. power supply voltage. figure 2-51: output leakage current vs. output voltage. -7 -6 -5 -4 -3 -2 -1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) negative power supply current; i ss (a) cal/cs = v dd +125c +85c +25c -40c 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output voltage (v) output leakage current (a) +25c +125c +85c cal/cs = v dd = 5.5v
? 2009-2011 microchip technology inc. ds22188c-page 21 mcp621/1s/2/3/4/5/9 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . table 3-1: pin function table mcp621 mcp621s mcp622 mcp623 mcp624 mcp625 mcp629 symbol description soic tdfn sot-23 soic dfn sot -23 soic tssop msop dfn qfn 22 4 22 4 2 2 22 1v in ?, v ina ? inverting input (op amp a) 33 3 33 3 3 3 33 2v in +, v ina + non-inverting input (op amp a) 7 7 5 8 8 6 4 4 10 10 3 v dd positive power supply ?? ? 55 ? 5 5 7 7 4 v inb + non-inverting input (op amp b) ?? ? 66 ? 66 885 v inb ? inverting input (op amp b) ?? ? 77 ? 77 996 v outb output (op amp b) ?? ? ?? ? ? ? ?? 7 cal bc /cs bc calibrate/chip select digital input (op amps b and c) ?? ? ?? ? 88 ?? 8 v outc output (op amp c) ?? ? ?? ? 99 ?? 9 v inc ? inverting input (op amp c) ?? ? ?? ? 10 10 ?? 10 v inc + non-inverting input (op amp c) 44 2 44 21111 44 11 v ss negative power supply ?? ? ?? ? 12 12 ?? 12 v ind + non-inverting input (op amp d) ?? ? ?? ? 13 13 ?? 13 v indd ? inverting input (op amp d) ?? ? ?? ? 14 14 ?? 14 v outd output (op amp d) ?? ? ?? ? ? ? ?? 15 cal ad /cs ad calibrate/chip select digital input (op amps a and d) 66 1 11 1 1 1 11 16 v out , v outa output (op amp a) ? 9 ? ? 9 ? ? ? 11 17 ep exposed thermal pad (ep); must be connected to v ss 88 ? ??5 ?? 55? cal/cs , cal a /cs a calibrate/chip select digital input (op amp a) ?? ? ?? ? ? ? 6 6 ? cal b /cs b calibrate/chip select digital input (op amp b) 55 ? ??? ????? v cal calibration common mode voltage input 1 1 ? ? ? ? ? ? ? ? ? nc no internal connection
mcp621/1s/2/3/4/5/9 ds22188c-page 22 ? 2009-2011 microchip technology inc. 3.1 analog outputs the analog output pins (v out ) are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs (v in +, v in ?, ?) are high-impedance cmos inputs with low bias currents. 3.3 power supply pins the positive power supply (v dd ) is 2.5v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors. 3.4 calibration common mode voltage input a low-impedance voltage placed at this input (v cal ) will set the op amps? common mode input voltage during calibration. if this pin is left open, the common mode input voltage during calibration is approximately v dd /3. the internal resistor divider is disconnected from the supplies whenever the part is not in calibration. 3.5 calibrate/chip select digital input this input (cal/cs , ?) is a cmos, schmitt-triggered input that affects the calibration and low-power modes of operation. when this pin goes high, the part is placed into a low-power mode and the output is high-z. when this pin goes low, a calibration sequence is started (which corrects v os ). at the end of the calibration sequence, the output becomes low-impedance and the part resumes normal operation. an internal por triggers a calibration event when the part is powered on, or when the supply voltage drops too low. thus, the mcp622 parts are calibrated, even though they do not have a cal/cs pin. 3.6 exposed thermal pad (ep) there is an internal connection between the exposed thermal pad (ep) and the v ss pin; they must be connected to the same potential on the printed circuit board (pcb). this pad can be connected to a pcb ground plane to provide a larger heat sink. this improves the package thermal resistance ( ja ).
? 2009-2011 microchip technology inc. ds22188c-page 23 mcp621/1s/2/3/4/5/9 4.0 applications the mcp621/1s/2/3/4/5/9 family of self-zeroed op amps is manufactured using microchip?s state-of-the- art cmos process. it is designed for low-cost, low- power and high-precision applications. its low supply voltage, low quiescent current and wide bandwidth makes the mcp621/1s/2/3/4/5/9 ideal for battery- powered applications. 4.1 calibration and chip select these op amps include circuitry for dynamic calibration of the offset voltage (v os ). 4.1.1 mcal calibration circuitry the internal mcal circuitry, when activated, starts a delay timer (to wait for the op amp to settle to its new bias point), then calibrates the input offset voltage (v os ). the mcal circuitry is triggered at power-up (and after some power brown-out events) by the internal por, and by the memory?s parity detector. the power-up time, when the mcal circuitry triggers the calibration sequence, is 200 ms (typical). 4.1.2 cal/cs pin the cal/cs pin gives the user a means to externally demand a low-power mode of operation, then to calibrate v os . using the cal/cs pin makes it possible to correct v os as it drifts over time (1/f noise and aging; see figure 2-35 ) and across temperature. the cal/cs pin performs two functions: it places the op amp(s) in a low-power mode when it is held high, and starts a calibration event (correction of v os ) after a rising edge. while in the low-power mode, the quiescent current is quite small (i ss = -3 a, typical). the output is also in a high-z state. during the calibration event, the quiescent current is near, but smaller than the specified quiescent current (2.5 ma, typical). the output continues in the high-z state, and the inputs are disconnected from the external circuit, to prevent internal signals from affecting circuit operation. the op amp inputs are internally connected to a common mode voltage buffer and feedback resistors. the offset is corrected (using a digital state machine, logic and memory), and the calibration constants are stored in memory. once the calibration event is completed, the amplifier is reconnected to the external circuitry. the turn-on time, when calibration is started with the cal/cs pin, is 5 ms (typical). there is an internal 5 m pull-down resistor tied to the cal/cs pin. if the cal/cs pin is left floating, the amplifier operates normally. for the mcp625 dual and the mcp629 quad, there is an additional constraint on toggling the two cal/cs pins close together; see the t con specification in table 1-3 . if the two pins are toggled simultaneously, or if they are toggled separately with an adequate delay between them (greater than t con ), then the cal/cs inputs are accepted as valid. if one of the two pins toggles, while the other pin?s calibration routine is in progress, then an invalid input occurs and the result is unpredictable. 4.1.3 internal por this part includes an internal power-on reset (por) to protect the internal calibration memory cells. the por monitors the power supply voltage (v dd ). when the por detects a low v dd event, it places the part into the low-power mode of operation. when the por detects a normal v dd event, it starts a delay counter, then triggers a calibration event. the additional delay gives a total por turn-on time of 200 ms (typical); this is also the power-up time (since the por is triggered at power up). 4.1.4 parity detector a parity error detector monitors the memory contents for any corruption. in the rare event that a parity error is detected (e.g., corruption from an alpha particle), a por event is automatically triggered. this will cause the input offset voltage to be recorrected, and the op amp will not return to normal operation for a period of time (the por turn-on time, t pon ). 4.1.5 calibration input pin a v cal pin is available in some options (e.g., the single mcp621) for those applications that need the calibration to occur at an internally driven common mode voltage other than v dd /3. figure 4-1 shows the reference circuit that internally sets the op amp?s common mode reference voltage (v cm_int ) during calibration (the resistors are disconnected from the supplies at other times). the 5k resistor provides overcurrent protection for the buffer. figure 4-1: common-mode reference?s input circuitry. to op amp during v cal buffer 5k 300 k 150 k v ss v dd calibration v cm_int
mcp621/1s/2/3/4/5/9 ds22188c-page 24 ? 2009-2011 microchip technology inc. when the v cal pin is left open, the internal resistor divider generates a v cm_int of approximately v dd /3, which is near the center of the input common mode voltage range. it is recommended that an external capacitor from v cal to ground be added to improve noise immunity. when the v cal pin is driven by an external voltage source, which is within its specified range, the op amp will have its input offset voltage calibrated at that common mode input voltage. make sure that v cal is within its specified range. it is possible to use an external resistor voltage divider to modify v cm_int ; see figure 4-2 . the internal circuitry at the v cal pin looks like 100 k tied to v dd /3. the parallel equivalent of r 1 and r 2 should be much smaller than 100 k to minimize differences in match- ing and temperature drift between the internal and external resistors. again, make sure that v cal is within its specified range. figure 4-2: setting v cm with external resistors. for instance, a design goal to set v cm_int =0.1v when v dd = 2.5v could be met with: r 1 =24.3k , r 2 =1.00k and c 1 = 100 nf. this will keep v cal within its range for any v dd , and should be close enough to 0v for ground-based applications. 4.2 input 4.2.1 phase reversal the input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-41 shows an input voltage exceeding both supplies with no phase inversion. 4.2.2 input voltage and current limits the esd protection on the inputs can be depicted as shown in figure 4-3 . this structure was chosen to protect the input transistors, and to minimize input bias current (i b ). the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick esd events within the specified limits. figure 4-3: simplified analog input esd structures. in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see section 1.1 ?absolute maximum ratings ?? ). figure 4-4 shows the recommended approach to protecting these inputs. the internal esd diodes prevent the input pins (v in + and v in ?) from going too far below ground, and the resistors r 1 and r 2 limit the possible current drawn out of the input pins. diodes d 1 and d 2 prevent the input pins (v in + and v in ?) from going too far above v dd , and dump any currents onto v dd . when implemented as shown, resistors r 1 and r 2 also limit the current through d 1 and d 2 . figure 4-4: protecting the analog inputs. it is also possible to connect the diodes to the left of the resistor r 1 and r 2 . in this case, the currents through the diodes d 1 and d 2 need to be limited by some other mechanism. the resistors then serve as in-rush current limiters; the dc current into the input pins (v in + and v in ?) should be very small. r 1 r 2 v ss v dd v cal c 1 mcp62x bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in ? v 1 r 1 v dd d 1 r 1 > v ss ? (minimum expected v 1 ) 2ma v out r 2 > v ss ? (minimum expected v 2 ) 2ma v 2 r 2 d 2 mcp62x
? 2009-2011 microchip technology inc. ds22188c-page 25 mcp621/1s/2/3/4/5/9 a significant amount of current can flow out of the inputs (through the esd diodes) when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-15 . applications that are high-impedance may need to limit the usable voltage range. 4.2.3 normal operation the input stage of the mcp621/1s/2/3/4/5/9 op amps use a differential pmos input stage. it operates at low common mode input voltage (v cm ), with v cm up to v dd ? 1.3v and down to v ss ? 0.3v. the input offset voltage (v os ) is measured at v cm =v ss ?0.3v and v dd ? 1.3v to ensure proper operation. see figure 2-6 and figure 2-7 for temperature effects. when operating at very low non-inverting gains, the output voltage is limited at the top by the v cm range (< v dd ?1.3v); see figure 4-5 . figure 4-5: unity gain voltage limitations for linear operation. 4.3 rail-to-rail output 4.3.1 maximum output voltage the maximum output voltage (see figure 2-16 and figure 2-17 ) describes the output range for a given load. for instance, the output voltage swings to within 40 mv of the negative rail with a 2 k load tied to v dd /2. 4.3.2 output current figure 4-6 shows the possible combinations of output voltage (v out ) and output current (i out ). i out is positive when it flows out of the op amp into the external circuit. figure 4-6: output current. 4.3.2.1 power dissipation since the output short circuit current (i sc ) is specified at 70 ma (typical), these op amps are capable of both delivering and dissipating significant power. two common loads, and their impact on the op amp?s power dissipation, will be discussed. figure 4-7 shows a resistive load (r l ) with a dc output voltage (v out ). v l is r l ?s ground point, v ss is usually ground (0v) and i out is the output current. the input currents are assumed to be negligible. figure 4-7: diagram for resistive load power calculations. the dc currents are: equation 4-1: the dc op amp power is: equation 4-2: the maximum op amp power, for resistive loads at dc, occurs when v out is halfway between v dd and v l , or halfway between v ss and v l : equation 4-3: v in v dd v out v ss v < in v , out v dd 1.3v ? mcp62x -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -80 -60 -40 -20 0 20 40 60 80 i out (ma) v out (v) r l = 10 ? r l = 100 ? r l = 2 k ? v oh limited v ol limited -i sc limited +i sc limited (v dd = 5.5v) v dd v out r l v l i dd i ss i out v ss mcp62x i out v out v l ? r l ------------------------- - = i dd i q max 0 i out , () + i ss i ? q min 0 i out , () + where: i q = quiescent supply current for one op amp (ma/amplifier) v out = a dc value (v) p oa i dd v dd v out ? () i ss v ss v out ? () + = max p oa () i dd v dd v ss ? () = max 2 v dd v l ? v l v ss ? , () 4r l ----------------------------------------------------------------- - +
mcp621/1s/2/3/4/5/9 ds22188c-page 26 ? 2009-2011 microchip technology inc. figure 4-7 shows a capacitive load (c l ), which is driven by a sine wave with dc offset. the capacitive load causes the op amp to output higher currents at higher frequencies. because the output rectifies i out , the op amp?s dissipated power increases (even though the capacitor does not dissipate power). figure 4-8: diagram for capacitive load power calculations. the output voltage is assumed to be: equation 4-4: the op amp?s currents are: equation 4-5: the op amp?s instantaneous power, average power and peak power are: equation 4-6: the power dissipated in a package depends on the powers dissipated by each op amp in that package: equation 4-7: the maximum ambient-to-junction temperature rise ( t ja ) and junction temperature (t j ) can be calculated using the maximum expected package power (p pkg ), ambient temperature (t a ) and the package thermal resistance ( ja ) found in table 1-4 : equation 4-8: the worst-case power derating for the op amps in a particular package can be easily calculated: equation 4-9: several techniques are available to reduce t ja for a given package: ? reduce ja - use another package - improve the pcb layout (ground plane, etc.) - add heat sinks and air flow ? reduce max (p pkg ) - increase r l - decrease c l - limit i out using r iso (see figure 4-9 ) - decrease v dd c l v dd v out i dd i ss i out v ss mcp62x v out v dc v ac t () sin + = where: v dc = dc offset (v) v ac = peak output swing (v pk ) = radian frequency (2 f) (rad/s) i out c l dv out dt ---------------- - ? v ac c l t () cos == i dd i q max 0 i out , () + i ss i ? q min 0 i out , () + where: i q = quiescent supply current for one op amp (ma/amplifier) p oa i dd v dd v out ? () i ss v ss v out ? () + = ave p oa () v dd v ss ? () i q 4v ac fc l ----------------------- - + ?? ?? = max p oa () v dd v ss ? () i q 2v ac fc l + () = p pkg p oa k1 = n = where: n = number of op amps in package (1 or 2) t ja p pkg ja = t j t a t ja + = p pkg t jmax t a ? ja -------------------------- where: t jmax = absolute maximum junction temperature (c) t a = ambient temperature (c)
? 2009-2011 microchip technology inc. ds22188c-page 27 mcp621/1s/2/3/4/5/9 4.4 improving stability 4.4.1 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. see figure 2-30 . a unity gain buffer (g = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 10 pf when g = +1), a small series resistor at the output (r iso in figure 4-9 ) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-9: output resistor, r iso stabilizes large capacitive loads. figure 4-10 gives recommended r iso values for different capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n ), where g n is the circuit?s noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n =+2v/v). figure 4-10: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot. modify r iso ?s value until the response is reasonable. bench evaluation and simulations with the mcp621/1s/2/3/4/5/9 spice macro model are helpful. 4.4.2 gain peaking figure 4-11 shows an op amp circuit that represents non-inverting amplifiers (v m is a dc voltage and v p is the input) or inverting amplifiers (v p is a dc voltage and v m is the input). the capacitances c n and c g represent the total capacitance at the input pins; they include the op amp?s common mode input capacitance (c cm ), board parasitic capacitance and any capacitor placed in parallel. figure 4-11: amplifier with parasitic capacitance. c g acts in parallel with r g (except for a gain of +1 v/v), which causes an increase in gain at high frequencies. c g also reduces the phase margin of the feedback loop, which becomes less stable. this effect can be reduced by either reducing c g or r f . c n and r n form a low-pass filter that affects the signal at v p . this filter has a single real pole at 1/(2 r n c n ). the largest value of r f that should be used depends on noise gain (see g n in section 4.4.1 ?capacitive loads? ) and c g . figure 4-12 shows the maximum recommended r f for several c g values. figure 4-12: maximum recommended r f vs. gain. figures 2-37 and 2-38 show the small signal and large signal step responses at g = +1 v/v. the unity gain buffer usually has r f =0 and r g open. figures 2-39 and 2-40 show the small signal and large signal step responses at g = -1 v/v. since the noise gain is 2 v/v and c g 10 pf, the resistors were chosen to be r f =r g =1k and r n =500 . r iso v out c l r g r f r n mcp62x 1 10 100 1,000 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 normalized capacitance; c l /g n (f) recommended r iso ( ? ) g n = +1 g n +2 1p 100p 1n 10n 10p v p r f v out r n c n v m r g c g mcp62x 1.e+02 1.e+03 1.e+04 1.e+05 110100 noise gain; g n (v/v) maximum recommended r f ( ? ) g n > +1 v/v 100 10k 100k 1k c g = 10 pf c g = 32 pf c g = 100 pf c g = 320 pf c g = 1 nf
mcp621/1s/2/3/4/5/9 ds22188c-page 28 ? 2009-2011 microchip technology inc. it is also possible to add a capacitor (c f ) in parallel with r f to compensate for the destabilizing effect of c g . this makes it possible to use larger values of r f . the conditions for stability are summarized in equation 4-10 . equation 4-10: 4.5 power supply with this family of operational amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good high-frequency performance. surface mount, multilayer ceramic capacitors, or their equivalent, should be used. these op amps require a bulk capacitor (i.e., 2.2 f or larger) within 50 mm to provide large, slow currents. tantalum capacitors, or their equivalent, may be a good choice. this bulk capacitor can be shared with other nearby analog parts as long as crosstalk through the supplies does not prove to be a problem. 4.6 high speed pcb layout these op amps are fast enough that a little extra care in the pcb (printed circuit board) layout can make a significant difference in performance. good pc board layout techniques will help you achieve the performance shown in the specifications and typical performance curves; it will also help you minimize emc (electro-magnetic compatibility) issues. use a solid ground plane. connect the bypass local capacitor(s) to this plane with minimal length traces. this cuts down inductive and capacitive crosstalk. separate digital from analog, low speed from high speed, and low power from high power. this will reduce interference. keep sensitive traces short and straight. separate them from interfering components and traces. this is especially important for high-frequency (low rise time) signals. sometimes, it helps to place guard traces next to victim traces. they should be on both sides of the victim trace, and as close as possible. connect guard traces to ground plane at both ends, and in the middle for long traces. use coax cables, or low inductance wiring, to route the signal and power to and from the pcb. mutual and self inductance of power wires is often a cause of crosstalk and unusual behavior. 4.7 typical applications 4.7.1 power driver with high gain figure 4-13 shows a power driver with high gain (1 + r 2 /r 1 ). the mcp621/1s/2/3/4/5/9 op amp?s short circuit current makes it possible to drive significant loads. the calibrated input offset voltage supports accurate response at high gains. r 3 should be small, and equal to r 1 ||r 2 , in order to minimize the bias current induced offset. figure 4-13: power driver. 4.7.2 optical detector amplifier figure 4-14 shows a transimpedance amplifier, using the mcp621 op amp, in a photo detector circuit. the photo detector is a capacitive current source. the op amp?s input common mode capacitance (9 pf, typical) and differential capacitance (2 pf, typical) act in paral- lel with c d . r f provides enough gain to produce 10 mv at v out . c f stabilizes the gain and limits the transimpedance bandwidth to about 0.51 mhz. r f ?s parasitic capacitance (e.g., 0.15 pf for a 0603 smd) acts in parallel with c f . figure 4-14: transimpedance amplifier for an optical detector. f f f gbwp 2g n2 () ? , g n1 g n2 < we need: g n1 1r f r g ? + = g n2 1c g c f ? + = f f 12 r f c f () ? = f z f f g n1 g n2 ? () = given: f f f gbwp 4g n1 () ? , g n1 g n2 > r 1 r 2 v in v dd /2 v out r 3 r l mcp62x photo detector c d c f r f v dd /2 30pf 100 k 3pf i d 100 na v out mcp621
? 2009-2011 microchip technology inc. ds22188c-page 29 mcp621/1s/2/3/4/5/9 4.7.3 h-bridge driver figure 4-15 shows the mcp622 dual op amp used as a h-bridge driver. the load could be a speaker or a dc motor. figure 4-15: h-bridge driver. this circuit automatically makes the noise gains (g n ) equal, when the gains are set properly, so that the frequency responses match well (in magnitude and in phase). equation 4-11 shows how to calculate r gt and r gb so that both op amps have the same dc gains; g dm needs to be selected first. equation 4-11: equation 4-12 gives the resulting common mode and differential mode output voltages. equation 4-12: r f r f v in v ot r f r gb v ob v dd /2 r gt r l ? mcp622 ? mcp622 g dm v ot v ob ? v in v dd 2 ? ? -------------------------------- 2 v / v r gt r f g dm 2 ? () 1 ? -------------------------------- - = r gb r f g dm 2 ? ------------------ - = v ot v + ob 2 --------------------------- v dd 2 ---------- - = v ot v ? ob g dm v in v dd 2 ---------- - ? ?? ?? =
mcp621/1s/2/3/4/5/9 ds22188c-page 30 ? 2009-2011 microchip technology inc. notes:
? 2009-2011 microchip technology inc. ds22188c-page 31 mcp621/1s/2/3/4/5/9 5.0 design aids microchip provides the basic design aids needed for the mcp621/1s/2/3/4/5/9 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp621/1s/2/3/4/5/9 op amps is available on the microchip web site at www.microchip.com . this model is intended to be an initial design tool that works well in the op amp?s linear region of operation over the temperature range. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchip?s filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the microchip web site at www.microchip.com/filterlab , the filter-lab design tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance. 5.3 microchip advanced part selector (maps) maps is a software tool that helps efficiently identify microchip devices that fit a particular design requirement. available at no cost from the microchip web site at www.microchip.com/maps , the maps is an overall selection tool for microchip?s product portfolio that includes analog, memory, mcus and dscs. using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase and sampling of microchip parts. 5.4 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demonstration and evaluation boards that are designed to help customers achieve faster time to market. for a complete listing of these boards and their corresponding user?s guides and technical information, visit the microchip web site at www.microchip.com/analog tools . some boards that are especially useful are: ? mcp6xxx amplifier evaluation board 1 ? mcp6xxx amplifier evaluation board 2 ? mcp6xxx amplifier evaluation board 3 ? mcp6xxx amplifier evaluation board 4 ? active filter demo board kit ? 8-pin soic/msop/tssop/ dip evaluation board, p/n soic8ev 5.5 application notes the following microchip application notes are available on the microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. ? adn003: ?select the right operational amplifier for your filtering circuits? (ds21821) ? an722: ?operational amplifier topologies and dc specifications? (ds00722) ? an723: ?operational amplifier ac specifications and applications? (ds00723) ? an884: ?driving capacitive loads with op amps? (ds00884) ? an990: ?analog sensor conditioning circuits ? an overview? (ds00990) ? an1177: ?op amp precision design: dc errors? (ds01177) ? an1228: ?op amp precision design: random noise? (ds01228) ? an1332: ?current sensing circuit concepts and fundamentals? (ds01332) some of these application notes, and others, are listed in the design guide: ? ?signal chain design guide? (ds21825)
mcp621/1s/2/3/4/5/9 ds22188c-page 32 ? 2009-2011 microchip technology inc. notes:
? 2009-2011 microchip technology inc. ds22188c-page 33 mcp621/1s/2/3/4/5/9 6.0 packaging information 6.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e device code mcp622t-e/mf dabl note: applies to 8-lead 3x3 dfn example: 5-lead sot-23 (mcp621s) 8-lead tdfn (2 x 3) (mcp621) example: 8-lead dfn (3x3) (mcp622) example 6-lead sot-23 ( mcp623 ) example xxnn yu xxnn b y 1 bl 11
mcp621/1s/2/3/4/5/9 ds22188c-page 34 ? 2009-2011 microchip technology inc. package marking information (continued) 14-lead soic (.150?) (mcp624) example 14-lead tssop (mcp624) 10-lead dfn (3x3) (mcp625) 10-lead msop (mcp625) example: device code mcp625t-e/mf bafa note: applies to 10-lead 3x3 dfn 8-lead soic (150 mil) (mcp621, mcp622) example: example example nnn mcp621 e sn ^^1129 256 3 e bafa 1129 256 625 eun 129256 mcp624 e/sl ^^ 1129256 3 e yyww nnn xxxxxxxx 624 e/st 1129 256 16-lead qfn (4x4) (mcp629) example pin 1 pin 1 629 e/ml ^^ 129256 3 e
? 2009-2011 microchip technology inc. ds22188c-page 35 mcp621/1s/2/3/4/5/9 n b e e1 d 1 2 3 e e1 a a1 a2 c l l1
mcp621/1s/2/3/4/5/9 ds22188c-page 36 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 37 mcp621/1s/2/3/4/5/9 6-lead plastic small outline transistor (chy) [sot-23] notes: 1. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.127 mm per side. 2. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 6 pitch e 0.95 bsc outside lead pitch e1 1.90 bsc overall height a 0.90 C 1.45 molded package thickness a2 0.89 C 1.30 standoff a1 0.00 C 0.15 overall width e 2.20 C 3.20 molded package width e1 1.30 C 1.80 overall length d 2.70 C 3.10 foot length l 0.10 C 0.60 footprint l1 0.35 C 0.80 foot angle 0 C 30 lead thickness c 0.08 C 0.26 lead width b 0.20 C 0.51 b e 4 n e1 pin 1 id by laser mark d 1 2 3 e e1 a a1 a2 c l l1 microchip technology drawing c04-028b
mcp621/1s/2/3/4/5/9 ds22188c-page 38 ? 2009-2011 microchip technology inc. 6-lead plastic small outline transistor (chy) [sot-23] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 39 mcp621/1s/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp621/1s/2/3/4/5/9 ds22188c-page 40 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 41 mcp621/1s/2/3/4/5/9
mcp621/1s/2/3/4/5/9 ds22188c-page 42 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 43 mcp621/1s/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp621/1s/2/3/4/5/9 ds22188c-page 44 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 45 mcp621/1s/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp621/1s/2/3/4/5/9 ds22188c-page 46 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 47 mcp621/1s/2/3/4/5/9
mcp621/1s/2/3/4/5/9 ds22188c-page 48 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 49 mcp621/1s/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp621/1s/2/3/4/5/9 ds22188c-page 50 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 51 mcp621/1s/2/3/4/5/9 d e e1 n note 1 1 2 b e a a1 a2 c l l1
mcp621/1s/2/3/4/5/9 ds22188c-page 52 ? 2009-2011 microchip technology inc. 10-lead plastic micro small outline package (un) [msop] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 53 mcp621/1s/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp621/1s/2/3/4/5/9 ds22188c-page 54 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 55 mcp621/1s/2/3/4/5/9
mcp621/1s/2/3/4/5/9 ds22188c-page 56 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 57 mcp621/1s/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp621/1s/2/3/4/5/9 ds22188c-page 58 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 59 mcp621/1s/2/3/4/5/9 d e n 2 1 exposed pad d2 e2 2 1 e b k n note 1 a3 a1 a l top view bottom view
mcp621/1s/2/3/4/5/9 ds22188c-page 60 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2011 microchip technology inc. ds22188c-page 61 mcp621/1s/2/3/4/5/9 appendix a: revision history revision c (august 2011) the following is the list of modifications: 1. added the mcp621s and mcp623 amplifiers to the product family and the related information throughout the document. 2. added the 2x3 tdfn (8l) package option for mcp621, sot-23 (5l) package for mcp621s and sot-23 (6l) package option for mcp623 and the related information throughout the document. 3. updated section 6.0 ?packaging informa- tion? with markings for the new additions. added the corresponding sot-23 (5l), sot-23 (6l) and 2x3 tdfn (8l) package options and related information. 4. updated table description and examples in product identification system . revision b (june 2011) the following is the list of modifications: 1. added the mcp624 and mcp629 amplifiers to the product family and the related information throughout the document. 2. added the corresponding soic (14l), tssop (14l) and qfn (16l) package options and related information. revision a (june 2009) ? original release of this document.
mcp621/1s/2/3/4/5/9 ds22188c-page 62 ? 2009-2011 microchip technology inc. notes:
? 2009-2011 microchip technology inc. ds22188c-page 63 mcp621/1s/2/3/4/5/9 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp621: single op amp mcp621t: single op amp (tape and reel) (soic) mcp621s: single op amp (sot-23) mcp622: dual op amp mcp622t: dual op amp (tape and reel) (dfn and soic) mcp623t: single op amp (tape and reel) (sot-23) mcp624: quad op amp mcp624t: quad op amp (tape and reel) (tssop and soic) mcp625: dual op amp mcp625t: dual op amp (tape and reel) (dfn and msop) mcp629: quad op amp mcp629t: quad op amp (tape and reel) (qfn) temperature range: e = -40c to +125c package: chy = plastic small outline (sot-23), 6-lead mf = plastic dual flat, no lead (3x3 dfn), 8-lead, 10-lead ml = plastic quad flat, no lead package (4x4 qfn), (4x4x0.9 mm), 16-lead mny = plastic dual flat, no lead (2x3 tdfn), 8-lead ot = plastic small outline (sot-23), 5-lead sn = plastic small outline, (3.90 mm), 8-lead st = plastic thin shrink small outline, (4.4 mm tssop), 14-lead sl = plastic small outline, narrow, (3.90 mm soic), 14-lead un = plastic micro small outline, (msop), 10-lead * y = nickel palladium gold manufacturing designator. only available on the tdfn package. examples: a) mcp621t-e/sn: tape and reel, extended temperature, 8ld soic package b) mcp621t-e/mny: tape and reel, extended temperature, 8ld tdfn package c) mcp621st-e/ot: tape and reel, extended temperature, 5ld sot-23 package d) mcp622t-e/mf: tape and reel, extended temperature, 8ld dfn package e) mcp622t-e/sn: tape and reel, extended temperature, 8ld soic package f) mcp623t-e/chy: tape and reel, extended temperature, 6ld sot-23 package g) mcp624t-e/sl: tape and reel, extended temperature, 14ld soic package h) mcp624t-e/st: tape and reel, extended temperature, 14ld tssop package i) mcp625t-e/mf: tape and reel, extended temperature, 10ld dfn package j) mcp625t-e/un: tape and reel, extended temperature, 10ld msop package k) mcp629t-e/ml: tape and reel, extended temperature, 16ld qfn package part no. - x /xx package temperature range device
mcp621/1s/2/3/4/5/9 ds22188c-page 64 ? 2009-2011 microchip technology inc. notes:
? 2009-2011 microchip technology inc. ds22188c-page 65 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009-2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-545-0 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds22188c-page 66 ? 2009-2011 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 08/02/11

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